Low voltage pulse system for addressing gas discharge display/memory panels

ABSTRACT

There is disclosed a low voltage pulse addressing system for addressing gas discharge display/memory panels wherein a portion of the pulse voltage is combined with the sustainer voltage so as to reduce the voltage required from each line drive pulsing circuit so as to permit utilization of low voltage integrated circuits.

United States Patent Johnson et al.

[ June 27, 1972 ADDRESSING GAS DISCHARGE DISPLAY/MEMORY PANELS Inventors:

Larry J. Schmersal, Toledo, Ohio 0wens-llllnols,- Inc.

Sept. 15, 1970 Assignee:

Filed:

Appl. No.:

LOW VOLTAGE PULSE SYSTEM FOR William E. Johnson, Temperance, Mich.;

U.S. CI. ..315/169 R, 315/169 TV, 315/260,

Int. Cl. ..H05b 37/02 Field of Search ..315/167, 169 R, 169 TV, 84.6,

315/260; 340/166 EL, 166 R References Cited UNITED STATES PATENTS 3,513,327 5/1970 Johnson ..315/169R Primary Examiner-Roy Lake Assistant Examiner-Siegfried H. Grimm AttorneyD. K. Wedding and E. J. Holler ABSTRACT There is disclosed a low voltage pulse addressing system for addressing gas discharge display/memory panels wherein a portion of the pulse voltage is combined with the sustainer voltage so as to reduce the voltage required from each line drive pulsing circuit so as to permit utilization of low voltage integrated circuits.

LOW VOLTAGE PULSE SYSTEM FOR ADDRESSING GAS DISCHARGE DISPLAY/MEMORY PANELS CROSS-REFERENCE TO RELATED APPLICATIONS The invention is related to the subject matter of Johnson et a1. application Ser. No. 699,170, filed Jan. 19, 1969; now US. Pat. No. 3,618,071 Schmersal application Ser. No. 851,131, filed July 18, 1969 now US. Pat. No. 3,628,088; Johnson ap plication Ser. No. 821,306, filed May 2, 1969 now US. Pat. No. 3,614,739, Schmersal application Ser. No. 888,741 filed Dec. 29, 1969 now U.S. Pat. No. 3,611,296 and Johnson application Ser. No. 888,743 filed Dec. 29, 1969, as well as a number of others owned by the common assignee hereof.

BACKGROUND OF THE INVENTION Gas discharge display/memory panels of the type to which the present invention pertains are disclosed in Baker et al. US. Pat. No. 3,499,167. Another example of a panel to which the invention is applicable is disclosed in an article by D.L. Bitzer et al. entitled, The Plasma Display Panel A Digitally Addressable Display With Inherent Memory, Proceedings of the Fall Joint Computer Conference IEEE, San Francisco, Calif, November 1966, pages 541-547. Panels as disclosed in the above-referenced patent and article have an electrical memory and such panels are capable of producing a visual display or representation of data and are characterized by an ionizable gaseous medium, usually a mixture of two gases at a selected pressure in a thin gas chamber or space between a pair of opposed dielectric charge storage members which are backed by row-column conductor matrix, each cross point of the matrix locating a discrete discharge volume in the gas which are locatable by the conductor matrix as described. The dielectric layers prevent the passage of any conductive current from the matrix conductor members to the gaseous medium and also serve as collecting surfaces for charges in the ionized gaseous medium during alternate half cycles of the periodic operating potentials supplied, such periodic operating potentials being designated as the sustainer potential. The discharge condition of the gas between selected row-column conductor pairs is controlled by application of discharge condition manipulating pulse potentials, preferably in the manner disclosed in our application Ser. No. 699,170 now US. Pat. No. 3,618,017. In the past, such pulse voltages have been relatively high and hence, generally require the utilization of high voltage circuits which, in integrated circuit fabrication, become, in a relative sense, expensive. The present invention is directed to the reduction of the transistor voltage requirement to permit utilization of a lower cost manufacturing technique when these circuits are made from integrated circuits. Thus, diode isolation techniques 'used to fabricate low voltage integrated circuits may be utilized in forming circuits to supply the discharge condition pulse manipulating voltages to a panel.

In accordance with the invention, an auxiliary low voltage pulse generator or source is combined with a sustainer source so that the pulser in series with each line to the panel may be a low voltage pulser circuit.

BRIEF DESCRIPTION OF THE DRAWING In the drawing:

FIG. 1 is block diagram showing in simplified partial plan view a display panel embodying the invention; and

FIG. 2 is a simplified wave form diagram to illustrate the principles of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INVENTION While a detailed description of a gas discharge display panel to which the invention is particularly applicable is found in the aforementioned Baker et al. U.S. Pat. No. 3,499,167, which is incorporated herein by reference, the panel is shown in simplified diagrammatic form in FIG. 1 as being composed of a row conductor plate 11 having row conductors R1, R2, RN on one surface thereof and a dielectric layer or coating 12 having a portion extending beyond the spacer sealant 13 which extends between the opposing column plate 14, carrying column conductors C1, C2, CN which, in a similar fashion have a dielectric coating or layer 16 thereon. Each of the row conductors R1, R2, RN has in series therewith a pulse voltage source 15-1, 15-2, 15-N, each of which receives a trigger pulse or trigger logic pulse LPR-l, LPR-2 LPR-N, respectively, from row decode logic circuit 18 which, in turn, receives information or data signals from data processing unit 19 which may be connected to a computer for receiving data on input terminal 20. Each row line pulser 15 is selectively operated by the logic pulses from row decode logic circuit 18 to supply discharge condition manipulating voltage pulses to selected row conductors. As illustrated, in FIG. 2, line (3), the row low voltage pulse produced by the low voltage pulser circuits in the row conductor lines are timed to occur simultaneously with the pulsing of an auxiliary row pulse generator 24 which received its trigger voltage from row decode logic 18 as illustrated. Row decode logic 18 provides I an output or trigger pulse to auxiliary row pulse generator 24 every time there is an output pulse on any one of the row decode logic output terminals LPRl LPR2, LPRN.

As further illustrated, the sustaining voltage for the row conductors is received from a row sustainer generator 25 which, in the embodiment illustrated is a sinusoidal voltage (FIG. 2, line 1) although square waves and triangular wave sustainer voltage wave forms may be used. As noted also, the common terminal between row sustainer voltage generator 25 and column sustainer voltage generator 26 is connected to a common ground terminal so that the row auxiliary pulse generator 24 as well as the row voltage pulsers are connected so as to electrically float on the output voltage wave form from sustaining generator 25. The sustaining generator disclosed in Murley application Ser. No 755,930 is well suited for this purpose.

In a similar fashion, the column conductors C1, C2, CN are each connected in series with a low voltage column pulser circuit 30-1, 30-2, 30-N each of which is adapted to receive and be triggered by a logic pulse from column decoder logic circuit 31. As shown, column decoder logic circuit 31 supplies a series of output pulses on lines LPCI, LPC2, LPCN in accordance with the information supplied thereto from data processing unit 19. In addition, any time a pulse appears on any one of terminals LPCl, LPC2, LPCN, a pulse appears on pulse output tenninal 34 which pulse is applied to column auxiliary pulse generator 33. This generator is identical to the pulse generator 24 and operates in a similar fashion. This pulse generator 33 is connected in series with column sustainer generator or source 35 which operates at phase relationship with respect to sustaining generator 25. Thus, as suming a sinusoidal voltage as is the case with sustaining voltage generator 25, its output voltage, and phase relationship with respect to the phase of the row sustainer voltage is shown on line 4 of FIG. 2. In addition, on line 5 of FIG. 2 is shown the pulse voltage from column auxiliary pulse generator 33 which is for purposes of simplicity shown as separated from the sustainer voltage wave form shown on line 4 of FIG. 2, but, in actuality the pulse shown on line 5 rides on" the column sustainer voltage as illustrated at 38. The column low voltage pulse output from generators 30-1, 30-2, 30-N, for one of these generators or sources, is shown on line 6 of FIG. 2. It should also be noted that the voltage pulses shown on lines 5 and 6 are negative relative to the voltage pulses shown on lines 2 and 3 which is in conformity with the column sustainer voltage being 180 out of phase with respect to the row sustainer. It will be appreciated further that on the next half cycle that the polarities would, relatively, be reversed. In addition, as in the case of the row conductor manipulating potentials, the column pulses are connected relative to the sustainer so as to electrically float on same.

Since the discharge unit located by the row-column conductor matrix are essentially voltage sensitive devices, the tum-on and tumxoff processes are both level dependent. Thus, in accordance with the invention, a portion of the control voltage pulses can be made a part of the sustainer-voltage without detracting from the operation of the panel. In this respect, the magnitude of this auxiliary pulse voltage (FIG. 2, lines 2 and 5) is such that it does not affect the discharge units which are on and discharge units which are ofi. However, when the sustainer auxiliary pulses are combined with a line voltage pulse from pulsers l5 and 30 in any selected pattern, then the voltage across a discharge unit will be sufficient to control the discharge conditions of same, either turning it on or turning it off. In this way, the row and column conductor voltage pulse requirements have been reduced greatly so as to thereby permit the use of low voltage integrated circuits which may be fabricated by the use of diode isolation techniques. In this way, the low voltage integrated circuit fabrication techniques of diode isolation can be utilized wherein the voltages are in or below the 60 volts range as compared to the higher voltage circuits which require dielectric isolation.

While a specific embodiment of the invention has been described for purposes of illustration, it will be understood that it is contemplated that many changes may be made without departing from the spirit and scope of the invention as set forth in the claims appended hereto.

What is claimed is:

1. In a system for supplying operating potentials to a gas discharge display and memory panel having insulated rowcolumn conductor matrix, said operating potentials including periodic sustainer voltages uniformly applied from a source to a selected number of row conductors and from said source, and at opposite phase, to a selected number of column conductors, respectively, and discharge condition manipulating voltage pulses selectively applied to selected row-column conductor pairs from row and column pulse voltage sources corresponding to each row and column conductor, respectively, the improvements comprising,

for said row conductors,

a further row pulse voltage source, means connecting said further pulse voltage source in series relation with said sustainer voltage for said row conductors and with each said row pulse source, said further row pulse voltage source being actuated once during a half cycle of said sustainer voltage and at a selected time period thereof, and v for said column conductors,

a further column pulse voltage source, means connecting said further pulse voltage source in series relation with the sustainer source for said column conductors and with each of said column pulse source, said further column pulse voltage source being actuated simultaneously with said further row pulse voltage source for said row conductors.

2. The invention defined in claim 1 wherein said further pulse voltage sources are pulsed simultaneously with the selective pulsing of said discharge condition manipulating rowcolumn pulse voltage sources.

3. The invention defined in claim 2, including logic circuit means controlling said pulse sources.

4. The invention defined in claim 1 wherein the voltage of said further pulse voltage sources and said row-column pulse voltage sources are connected relative to said sustainer voltages, respectively, so as to electrically float on same, respectively. 

1. In a system for supplying operating potentials to a gas discharge display and memory panel having insulated row-column conductor matrix, said operating potentials including periodic sustainer voltages uniformly applied from a source to a selected number of row conductors and from said source, and at opposite phase, to a selected number of column conductors, respectively, and discharge condition manipulating voltage pulses selectively applied to selected row-column conductor pairs from row and column pulse voltage sources corresponding to each row and column conductor, respectively, the improvements comprising, for said row conductors, a further row pulse voltage source, means connecting said further pulse voltage source in series relation with said sustainer voltage for said row conductors and with each said row pulse source, said further row pulse voltage source being actuated once during a half cycle of said sustainer voltage and at a selected time period thereof, and for said column conductors, a further column pulse voltage source, means connecting said further pulse voltage source in series relatIon with the sustainer source for said column conductors and with each of said column pulse source, said further column pulse voltage source being actuated simultaneously with said further row pulse voltage source for said row conductors.
 2. The invention defined in claim 1 wherein said further pulse voltage sources are pulsed simultaneously with the selective pulsing of said discharge condition manipulating row-column pulse voltage sources.
 3. The invention defined in claim 2, including logic circuit means controlling said pulse sources.
 4. The invention defined in claim 1 wherein the voltage of said further pulse voltage sources and said row-column pulse voltage sources are connected relative to said sustainer voltages, respectively, so as to electrically float on same, respectively. 